data/verilog-mode-20161124.fd230e6/.gitignore: ASCII text data/verilog-mode-20161124.fd230e6/0test.el: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/LICENSE: ASCII text data/verilog-mode-20161124.fd230e6/Makefile: ASCII text data/verilog-mode-20161124.fd230e6/README: ASCII text data/verilog-mode-20161124.fd230e6/TODO: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/attic/verilog-lex.el: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/batch_prof.el: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/batch_test.el: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/batch_test.pl: Perl script text executable data/verilog-mode-20161124.fd230e6/config_rev.pl: Perl script text executable data/verilog-mode-20161124.fd230e6/error_file.v: ASCII text data/verilog-mode-20161124.fd230e6/error_msgs.out: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/make_log.pl: Perl script text executable data/verilog-mode-20161124.fd230e6/make_mail.pl: Perl script text executable data/verilog-mode-20161124.fd230e6/makechangelog: Perl script text executable data/verilog-mode-20161124.fd230e6/tests/abc.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/auto_delete_whitespace.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_comment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_jwells_comment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_quote_cmt.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_single.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_sort_fedeli.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_string_bug259.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoarg_supply_bug438.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoascii_myers.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan_inc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_auto.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_ex.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_frominc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_onehot.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_reed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoconst_gesmith.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoconstant_gooch.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinout.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinout_lovell.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinout_ma.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinout_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutcomp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutin.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodport_bourduas_type.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule_iface.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule_iface_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule_ign.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule_re2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule_v2k.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinoutparam.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_array_bug294.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_asharma.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_asharma_v2k.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_concat_ignore.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_concat_lau.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_concat_lau2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_none.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinput_paren.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinsertlast_1.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_2k_fredriksen.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_ams_vorwerk.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_array.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_array_braket.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_atregexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_belkind_concat.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba_gi.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_brucet.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_brucet_library.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_bug373.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_case_chakradhara.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_casefold_hou.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_cavanaugh_pull.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_ciu.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_clog2_bug522.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_cmtcell_msg270.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_cmtinst_bug383.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_cmtparen_tennant.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_crawford_array.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_crawford_array_a.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_dedefine.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_ding.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_for_myers.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_func.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_gate.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_genvar.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_iface270_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_iface270_top.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_iface270_top_bug429.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_ifdef_fredrickson_200503_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_ifdef_fredrickson_200503_top.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_import.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_instname_all.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_instname_carlh.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_interface.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_interface_bug320.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_interface_star.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_interface_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_johnson.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_lopaz.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_lopaz_srpad.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_ma_io_prefix.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_mccoy.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_moddefine.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_modport_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_mplist.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_mplist_child.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_mplist_mbl_if.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_multidim.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_multitemplate.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_name_bug245.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_nicholl.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_overflow_bug250.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_param_2d.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_param_cmt.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_param_type.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_paramvalue.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_podolsky.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_precomment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_rao.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_regexp_match.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_rogoff.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_rons.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_signed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_signed_fubar.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_signed_fubar2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_star.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_sv_kulkarni.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_sv_kulkarni_base.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_sv_kulkarni_wire.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_sv_shaw.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_template_lint.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_tennant.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_unsigned_bug302.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_vertrees.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_vertrees_slv.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_vkadamby.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_width.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcell.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_belkind.v-dontrun: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_belkind_leaf.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_bug287.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_first.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_first_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_iface_bruce.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_int.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoinstparam_local.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autolisp_include.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autolisp_include_inc.vh: ASCII text data/verilog-mode-20161124.fd230e6/tests/autolisp_order_bug356.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autolisp_truex.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/autologic.sv: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/automodport_ex.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/automodport_full.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/automodport_if.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autooutput_comma.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autooutput_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autooutputevery_assign.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autooutputevery_example.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autooutputevery_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autooutputevery_wire.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreg_outreg.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreg_smith_multiassign.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreginput.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_assert.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_cond.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_define_colon.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_dever.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_eq_bug381.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_eq_bug381_non.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_equal_extra.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_if.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_ifndef_dc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_inf_bug325.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_label_gorfajn.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_latch.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_reed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_struct.v: Java source, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_widths.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests/autoreset_widths_unbased.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_aas_ifdef.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_add_or.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_chadha.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_define_hang.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_dittrich.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_dittrich_inc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_gifford.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_if_else.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_inandout.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_inc_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_jbrown.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_lavinge.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_mcardle_onehot.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_metzger_space.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_one.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_peers_func.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_rogoff.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_smith.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autosense_venkataramanan_begin.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autotieoff_assign.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autotieoff_signed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autoundef.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autounused.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_godiwala.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_import_bug317.v: Perl5 module source, ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_isaacson.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_long_yaohung.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_lovell_hiear.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_merge_bug303.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_misalias_bug295.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_myers.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_nocomment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_paramvec_bug302.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_pkg_bug195.v: Perl5 module source, ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_real.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_req.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_req_sw.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_thon_selects.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/autowire_totte.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/batch_li_child.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/batch_li_parent.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/batch_prof_cell.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/carlson.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/case_question.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/comment_strip.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/debug.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/disable.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/escape_a.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/escape_top.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/example.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/flag_f_reeves.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/flag_f_reeves.vc: ASCII text data/verilog-mode-20161124.fd230e6/tests/for.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/gorfajn.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/grisamore_twoinone.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/hangcase.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_1.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_3.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_4.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_always_decl.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_assert.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_assert_else.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_assert_property.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_assignment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_attributes.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_begin_clapp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_bracket.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_case.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_class.v: C source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_clocking.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_clockingblock.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_comments.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_constraint.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_constraint2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_constraint3.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_covergroup.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_coverpoint.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_decl-1.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_decl.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_directives.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_dpi.v: Perl5 module source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_foreach.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_fork_join_any.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_formfeed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_function.v: C++ source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_generate.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_if.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_if2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_ifdef.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_ifdef_generate.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_immediate_assertion.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_importfunction.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_interface.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_linefeed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_lineup_inlists.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_lineup_mode_all.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_lineup_mode_assignments.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_lineup_mode_declarations.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_lineup_mode_none.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_macro_braces.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_macro_comment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_mailbox.v: C++ source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_modansi.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_modport.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_named_assert.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_ovm.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_preproc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_preproc_label.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_property.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_randcase.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_random.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_struct.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_task.v: C++ source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_task_func_decl.sv: C++ source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_typedef.sv: Perl5 module source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_unique_case-1.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_unique_case-2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_unique_case.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_uvm.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_virtual_class.sv: C++ source, ASCII text data/verilog-mode-20161124.fd230e6/tests/indent_warren.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_first.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_inst_empty_ports.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_inst_endparen.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_inst_net_case.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_inst_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_path.f: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_path.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_path_cmt.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inject_path_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/inst.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_always.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_class.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_do.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_function.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_macro.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_no_indent.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/label_task.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/lavigne_instpath.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/lavigne_instpath/lavigne_t1.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/lavigne_instpath/lavigne_t2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/lineup.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/local_vmode.x: ASCII text data/verilog-mode-20161124.fd230e6/tests/local_vmode_sub.x: ASCII text data/verilog-mode-20161124.fd230e6/tests/mac_autosense_dot.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/mac_test2.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/mac_test2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/more_params.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests/morrison.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/params_multiline_msg618.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/params_multiline_msg618_inc.vh: ASCII text data/verilog-mode-20161124.fd230e6/tests/property_test.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/reversed_bits.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/set_membership.sv: Java source, ASCII text data/verilog-mode-20161124.fd230e6/tests/singh.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/sol_asense.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/src_frag.vs: C++ source, ASCII text data/verilog-mode-20161124.fd230e6/tests/subdir/flag_f_reeves_IBUF.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/sv_import.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/t_autoinst_def_clk.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/task.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/testcase.sv: C source, ASCII text data/verilog-mode-20161124.fd230e6/tests/testcases.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/tss_max32.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/two_modules.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_inst_hicks.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_localparam.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_signed_kundsen.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_typedef_yee.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_typedef_yee_inc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_typedef_yee_sub1.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/v2k_typedef_yee_sub2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/verilint_113.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/vmm_regressions.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests/wasson.v: ASCII text data/verilog-mode-20161124.fd230e6/tests/xx.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinst_lopaz.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinst_star.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_batch_ok/batch_li_parent.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/.gitignore: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/abc.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/auto_delete_whitespace.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_comment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_jwells_comment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_quote_cmt.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_single.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_sort_fedeli.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_string_bug259.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_supply_bug438.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_myers.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan_inc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_auto.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_ex.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_frominc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_onehot.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_reed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoconst_gesmith.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoconstant_gooch.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_lovell.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_ma.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutcomp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutin.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodport_bourduas_type.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_iface.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_iface_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_ign.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_re2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_v2k.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutparam.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_array_bug294.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_asharma.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_asharma_v2k.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_ignore.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_none.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_paren.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinsertlast_1.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_2k_fredriksen.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_ams_vorwerk.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_array.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_array_braket.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_belkind_concat.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba_gi.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_brucet.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_brucet_library.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_bug373.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_case_chakradhara.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_casefold_hou.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_cavanaugh_pull.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_ciu.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_clog2_bug522.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_cmtcell_msg270.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_cmtinst_bug383.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_cmtparen_tennant.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_crawford_array.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_crawford_array_a.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_dedefine.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_ding.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_for_myers.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_func.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_gate.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_genvar.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_iface270_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_iface270_top.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_iface270_top_bug429.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_ifdef_fredrickson_200503_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_ifdef_fredrickson_200503_top.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_import.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_all.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_carlh.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_bug320.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_star.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_johnson.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz_srpad.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_ma_io_prefix.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_mccoy.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_moddefine.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_modport_param.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist_child.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist_mbl_if.sv: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_multidim.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_multitemplate.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_name_bug245.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_nicholl.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_overflow_bug250.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_param_2d.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_param_cmt.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_param_type.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover_sub.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramvalue.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_podolsky.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_precomment.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_rao.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_rogoff.v: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_rons.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_signed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_signed_fubar.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_signed_fubar2.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_star.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_sv_kulkarni.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_sv_kulkarni_base.v: ASCII text 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data/verilog-mode-20161124.fd230e6/tests_ok/autologic.sv: Lisp/Scheme program, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/automodport_ex.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/automodport_full.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/automodport_if.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autooutput_comma.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autooutput_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_assign.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_example.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_regexp.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autooutputevery_wire.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoreg_outreg.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoreg_smith_multiassign.v: ASCII text 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data/verilog-mode-20161124.fd230e6/tests_ok/autoreset_reed.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoreset_struct.v: Java source, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoreset_widths.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autoreset_widths_unbased.v: Ruby script, ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_aas_ifdef.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_add_or.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_chadha.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_define_hang.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_dittrich.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_dittrich_inc.v: ASCII text data/verilog-mode-20161124.fd230e6/tests_ok/autosense_gifford.v: ASCII text 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